module Uart
(
  clk_50,rst,uart_rx,
  uart_tx,out_rx_data
);

input		clk_50;
input		rst;
input		uart_rx;
output	uart_tx;
output   [7:0]out_rx_data;

wire		clk_100;
wire		rx_bps_start;
wire		rx_bps_flag;
wire		tx_bps_start;
wire		tx_bps_flag;

PLL	PLL_inst 
(
	.inclk0 (clk_50),
	.c0 (clk_100)
);
	
Uart_bps Uart_rx_bps
(
	.clk_100(clk_100),
	.rst(rst),
	.bps_start(rx_bps_start),
	.bps_flag(rx_bps_flag)
);

Uart_rx_module Uart_rx_module
(
	.clk_100(clk_100),
	.rst(rst),
	.uart_rx(uart_rx),
	.rx_bps_start(rx_bps_start),
	.rx_bps_flag(rx_bps_flag),
	.out_rx_data(out_rx_data)
);

endmodule
	